Behavioral Simulation Techniques for Substrate Noise Analysis in PLL Circuits

This paper presents a methodology to simulate, at the system level, the substrate noise coupling to phase locked loop (PLL) circuits in mixed signal systems. Macro-modeling for digital noise injection and propagation through the substrate are considered. Behavioral models of the PLL for noise sensing as well as intrinsic functionality are abstracted from transistor level circuit analysis results. An impulse sensitivity function (ISF) technique is proposed to characterize the substrate noise effects on the phase perturbation of the voltage controlled oscillator (VCO). Verification uses time-domain analysis with a simulator and abstracted behavioral models, all implemented in the C++ language. Compared to the traditional circuit level simulation method, this approach provides several orders-ofmagnitude improvement in speed with acceptable accuracy in terms of phase noise spectra.